1. Field
Example embodiments relate to a vertical pillar transistor and a method of manufacturing the vertical pillar transistor. More particularly, example embodiments relate to a vertical pillar transistor having a uniform channel length and a method of manufacturing the vertical pillar transistor.
2. Description of the Related Art
As semiconductor devices are becoming highly integrated, line widths of patterns of the semiconductor devices and distances between the patterns are sharply decreasing. When the line widths of the patterns are reduced, channel lengths of transistors of the semiconductor devices are also reduced. However, when a transistor has a channel length that is smaller than that required for effective operation of the transistor, a short channel effect may be generated. As a result, electrical characteristics of the transistor may sharply deteriorate. Accordingly, transistors having various structures are being developed in order to obtain sufficient channel lengths. For example, a vertical pillar transistor, in which a pillar protruding substantially perpendicular to a substrate is used as a channel, is being developed. When forming the vertical pillar transistor, a space between adjacent pillars is filled with an insulation material, and the insulation material is partially removed for forming a word line in a subsequent process. However, as semiconductor devices have become highly integrated, distances between adjacent pillars have become reduced. Accordingly, when a vertical pillar transistor is manufactured through a conventional art, an insulation material may not be clearly removed in a removing process for partially removing the insulation material. As a result, a channel may not have a uniform length, and a bridge may be generated between word lines.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method of forming a vertical pillar transistor. Referring to FIG. 1, a plurality of pillar structures may be formed. The pillar structure may include a lower pillar 15, an upper pillar 20, a pad oxide layer 25, a hard mask 30, an oxide layer 35 and a spacer 40. After forming the lower pillar 15 and the upper pillar 20 on a substrate 10, the pad oxide layer 25 and the hard mask 30 are sequentially stacked on the upper pillar 20. The oxide layer 35 covering the upper pillar 20, the pad oxide layer 25 and the hard mask 30 may be formed. An impurity region 45 may be formed adjacent to a region between the lower pillar 15 and the upper pillar 20.
Referring to FIG. 2, a gap between the pillar structures may be filled with an insulation material 50, for example, inorganic spin-on glass (SOG) (e.g., Tonen Silazene (TOSZ)), which is a polysilazane material. The insulation material 50 may electrically insulate the adjacent pillar structures and the adjacent impurity regions 45 from each other, respectively. When the TOSZ layer is used as the insulation material 50, an annealing process may be performed to reduce the fluidity of the TOSZ layer, so that the TOSZ layer is hardened. When the gap has a deep depth, the annealing process may not have a sufficient effect on a lower portion of the TOSZ layer. Accordingly, the TOSZ layer may not be uniformly hardened, for example, the lower portion of the TOSZ layer may not be sufficiently hardened.
Referring to FIG. 3, the insulation material 50 may be partially removed to form an insulation layer 55, so that an upper face of the insulation layer 55 may be disposed in the gap between the pad oxide layer 25 and an upper portion of the lower pillar 15. When the insulation layer 55 is not uniformly hardened, the insulation layer 55 may have an irregular etching profile between the pillar structures or be over-etched by an etching process. When a word line is formed on the insulation layer, the word line may not be uniformly formed. Accordingly, a semiconductor device having the word line may have undesirable reliability.